1. Field of the Invention
The invention relates to serial access memories. More particularly, it relates to electrically erasable programmable read-only memories (EEPROMs), although it can be applied to other types of volatile or non-volatile memories.
2. Discussion of the Related Art
The current development of memories in integrated circuit form with very large information storage capacities (in terms of the number of information elements stored) is being accompanied by the desire to increase the frequencies of the clock signal that sets the rate of operation of the systems in which these memories are implemented. Consequently, there is also a search for increasingly shorter times for gaining access to the contents of the words stored in these memories. The term "word" is understood to mean a physical entity whose contents represent a binary information element encoded on b bits, where b is an integer. Typically, these words will be formed by b elementary storage cells, each elementary cell being typically formed by a storage circuit.
From the viewpoint of access time, parallel access memories are the most advantageous ones. A period corresponding to one cycle of the clock signal that sets the rate of operation of such a memory is enough to provide one of these memories, in parallel, with the address of the word whose contents are to be read.
Nevertheless, serial access memories also have definite advantages as compared with parallel access memories, such as lower manufacturing cost, and overall have appreciably smaller bulk and weight. Indeed, serial access memories require a far smaller number of connection pins. The number of connection pins for an integrated circuit greatly affects the mount of space taken up by the circuit. Consequently, serial access memories are very valuable in portable applications.
It would be desirable to be able to increase the clock signal frequencies and the storage capacities of serial access memories. The best performing products at present have capacities of 64 kilobits and work at frequencies in the range of 1 megahertz. In the near future, capacities of the order of 256 kilobits and frequencies in the range of 5 megahertz and more can be envisaged.
In practice, increasing the clock signal frequencies of these memories raises technical problems essentially related to the time of access, in read mode, of the contents of the words stored in the memories. The term "access time" is understood to mean the period, between the point in time when the address of a word is known to the memory (namely the point in time when all the address bits of this word have been received serially by the memory), and the point in time when the binary information that the contents of the cells that the word represent starts being available (if the memory is a series output memory), or is available (if the memory is a parallel output memory or if the information elements are encoded on one bit), outside the memory by means of one or more output pins.
The access time is limited by the time needed to sequence the following two steps:
decoding of the address received by the memory, specifically the positioning of various switch-over devices that connect a read circuit to the word whose contents represent the binary information to be read, and PA1 the reading process, i.e., the extraction of the binary information in the form of logic signals according to the word read (the cells of the word do not necessarily store a directly usable logic information element but more generally have a variable physical characteristic that an appropriate circuit, for example a differential amplifier, will convert into a logic signal). PA1 the series reception of the q first bits of the address of the word to be read, q being an integer smaller than k, PA1 in parallel with the reception of k-q last bits of the address: PA1 the decoding of the k-q last bits of the address of the word to be read, and supplying at a data output terminal of the memory, the binary information element that is represented by the contents of the word whose address bits correspond to the k address bits received.
In a standard way the address, which is encoded on a certain number of bits, is received serially in a shift register. This process lasts for as many clock signal cycles as there are address bits to be received.
The maximum permissible access time is often equal to the duration of an odd number of clock signal half-cycles. For example, this access time is set at three half-cycles if the memory is connected to a Microwire or I2C type bus and is set at one half-cycle if the memory is connected to an SPI bus.
The type of bus by which the memory communicates with other devices therefore sets the maximum permissible access time for a given clock signal frequency. For example, if it is desired to use an SPI bus and a clock signal frequency of 2 megahertz, the permissible access time is limited to 250 nanoseconds, which corresponds to a level of performance close to those devices for reading fast parallel access memories.
There are, however, technical difficulties of construction inherent in the required switch-over speeds. The circuits used are often high power consumption circuits. This is hardly desirable for memories that are often designed for portable applications for which a minimum level of power consumption is sought. In practice, therefore, the frequency of the clock signal and the type of bus used determine the maximum permissible access time.